An all digital phase-locked loop (ADPLL) is a digital circuit with a digitally controlled oscillator (DCO) which can be periodically adjusted so that the DCO's output phase tracks the phase (and hence, the frequency) of a reference signal.
High bandwidth PLLs are usually built as type-I PLLs (featuring one pole at dc) due to a type-I PLL's inherently larger bandwidth (when compared to type-II and higher order PLLS). The larger bandwidth permits the type-I PLL to more rapidly acquire the desired signal. Unfortunately, the large bandwidth afforded by the type-I PLL comes at the expense of enhanced phase noise and spurs. During rapid acquisition, the enhanced phase noise and spurs are of little consequence, but after the desired signal has been acquired and the goal becomes maintaining and tracking the desired signal, it is desired that phase noise and spurs be minimized. This may be achieved by reducing loop gain, hence reducing overall bandwidth. A type-I PLL can provide faster dynamics by avoiding the use of a loop filter.
To provide good performance in the face of seemingly conflicting requirements, a PLL that operates in two distinct intervals can be used. In a first interval (a rapid signal acquisition interval) the PLL may operate with a maximum bandwidth to minimize signal acquisition time. The first interval may then be followed by a second interval (a signal tracking interval) wherein the PLL can minimize its bandwidth to reduce phase noise and spurs.
In one solution, a first loop gain value is used during the rapid signal acquisition interval of PLL operation. The first loop gain value may be a relatively large value, with a constraint being that the PLL's phase error remains within acceptable limits. After the signal has been acquired, the loop gain value may then be changed to a second loop gain value, wherein the second loop gain value is smaller than the first loop gain value. The loop gain may be changed when a developed phase error (which is a rough indication of a frequency offset in a type-I loop) has reached a steady-state value.
One disadvantage of the prior art is that the abrupt switch from a first loop gain value to a second loop gain value may introduce significant transients into the phase error, which with the loop's reduced bandwidth (due to the decreased loop gain value) may take an extended amount of time to settle.